The present invention generally relates to semiconductor devices, and particularly to the manufacture of epitaxially-grown source/drains of multi-fin finFETs.
Fin metal-oxide-semiconductor field effect transistor (Fin-MOSFET) is an emerging technology which provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at, and below, the 22 nm node. FinMOSFET structures include fin field effect transistors (finFETs) which include at least one narrow semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. FinFET structures may be formed on a semiconductor-on-insulator (SOI) substrate, because of the low source/drain diffusion, low substrate capacitance, and ease of electrical isolation by shallow trench isolation structures.
FinFET devices having multiple fins covered by a single gate (also known as multigate devices) have been developed to further maximize the surface area contact between the body region of the fins and the gate. The multiple fins of multigate devices may be merged on one end to form a single source/drain region. Merging the multiple fins may be accomplished by epitaxially grown source/drain material, such as silicon, on the fin surface. However, as semiconductor devices continue to decrease in size, the smaller spaces between the fins may lead to issues such as faceting when growing source/drain regions of multigate devices. Due to the nature of epitaxial growth and certain structural features of integrated circuit devices, faceting is the result of epitaxially grown regions exhibiting undesirably formed shapes that impact device performance and reliability. In the case of forming source/drain regions on SOI finFETs, epitaxial growth occurs primarily on the fin sidewalls. Sidewall growth can result in faceting, voids, and other defects where growths on opposing sidewalls meet. Therefore, a method of growing source/drain regions of multigate devices that may, among other things, avoid faceting is desirable.